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Silicon Bipolar RFIC 900 MHz Vector Modulator Technical Data
HPMX-2003
Features
* 800-1000 MHz Output Frequency Range * +6 dBm Peak Pout * Unbalanced 50 Output * Internal 90 Phase Shifter * 5 Volt, 36 mA Bias * SO-16 Surface Mount Package
Plastic SO-16 Package
Description
Hewlett Packard's HPMX-2003 is a Silicon RFIC direct conversion vector modulator designed for use at output frequencies between 800 MHz and 1 GHz. Housed in a SO-16 surface mount plastic package, the IC contains two matched Gilbert cell mixers, an RC phase shifter, a summer, and an output amplifier complete with 50 impedance match and DC block. This device is suitable for use in direct and offset-loop modulated portable and mobile telephone handsets for cellular systems such as GSM, North American Digital Cellular and Japan Digital Cellular. It can also be used in digital transmitters operating in the 900 MHz ISM (Industrial-Scientific-Medical) band, including use in Local Area Networks (LANs). The HPMX-2003 is fabricated with Hewlett-Packard's 25 GHz ISOSAT-II process, which combines stepper lithography, ion-implantation, self-alignment techniques, and gold metallization to produce RFICs with superior performance, uniformity and reliability.
Applications
* Direct Modulator for 900 MHz Cellular Telephone Handsets, Including GSM, JDC, and NADC * Direct Modulator for 900 MHz ISM Band SpreadSpectrum Transmitters and LANs
Pin Configuration
V CC 1 V CC 2 GROUND 3 GROUND 4 Qref 5 Qmod 6 LOin 7 LOgnd 8 16 VCCL 15 RFout 14 GROUND 13 GROUND 12 Iref 11 Imod 10 GROUND 9 DO NOT CONNECT
Functional Block Diagram
I MIXER
Imod Iref 0
VCC VCCL
LO + LO -
90
PHASE SHIFTER
SUMMER OUTPUT AMPLIFIER
*
RFout 50 ZO unbalanced
Qref Qmod
Q MIXER
5965-9103E
7-38
HPMX-2003 Absolute Maximum Ratings, TA = 25C
Symbol Pdiss LOin VCC VImod, VQmod VIref, VQref TSTG Tj Parameter Power Dissipation[2,3] LO Input Power Supply Voltage Swing of VImod about VIref[4] or VQmod about VQref Reference Input Levels[4] Storage Temperature Junction Temperature Units mW dBm V Vp-p V C C Absolute Maximum[1] 500 15 10 5[4] 5[4] -65 to +150 150 Thermal Resistance[2]: jc =125C/W
Notes: 1. Operation of this device above any one of these parameters may cause permanent damage. 2. TC = 25C (TC is defined to be the temperature at the end of pin 3 where it contacts the circuit board). 3. Derate at 8 mW/C for TC > 88C. 4. Do not exceed VCC by more than 0.8 V.
HPMX-2003 Guaranteed Electrical Specifications, TA = 25C, ZO = 50 VCC = 5 V, LO= -12 dBm at 900 MHz (Unbalanced Input), VIref = VQref = 2.5 V (Unless Otherwise Noted).
Symbol Id Pout LOleak mod Parameters and Test Conditions Device Current Output Power Pout - LO at Output Average Modulation Error (V VImod = VQmod = 3.75 V VImod = VQmod = 2.5 V
2 2 Imod - 2.5) + (VQmod - 2.5)
Units mA dBm dBc %
Min.
Typ. 36
Max. 44
+4.0 +30
+ 6 +37 4 7
= 1.25 V
HPMX-2003 Summary Characterization Information, TA = 25C, ZO = 50
VCC = 5 V, LO = -12 dBm at 900 MHz (Unbalanced Input), VIref = VQref = 2.5 V (Unless Otherwise Noted). Symbol Rin Rin-gnd VSWRLO Parameters and Test Conditions Input Resistance (Imod to Iref or Qmod to Qref) Input Resistance to Ground (Any I, Q Pin to Ground) LO VSWR (50 ) GSM: 890-915 MHz Bandwidth NADC: 824-850 MHz Bandwidth JDC: 940-960 MHz Bandwidth GSM: 890-915 MHz Bandwidth NADC: 824-850 MHz Bandwidth JDC: 940-960 MHz Bandwidth VImod = VQmod = 3.75 V IM3 Ai Pi DSB Third Order Intermodulation Products RMS Amplitude Error RMS Phase Error 7-39 dBm/Hz dBc dB degrees Units Typ. 10 k 10 k 1.5:1 1.5:1 1.5:1 1.2:1 1.1:1 1.2:1 -134 +34 0.3 2
VSWRO
Output VSWR (50 ) (Tuned by Placement of VccL Capacitor - See Figures 22, 32, and 42) Output Noise Floor
HPMX-2003 Pin Description
VCC (pins 1,2) These two pins provide DC power to the mixers in the RFIC, and are connected together internal to the package. They should be connected to a 5 V supply, with appropriate AC bypassing (1000 pF typ.) used near the pins, as shown in figures 1 and 2. The voltage on these pins should always be kept at least 0.8 V more positive than the DC level on any of pins 5, 6, 11, or 12. Failure to do so may result in the modulator drawing sufficient current through the data or reference inputs to damage the IC. Ground (pins 3, 4, 10, 13 & 14) These pins should connect with minimal inductance to a solid ground plane (usually the backside of the PC board). Recommended assembly employs multiple plated through via holes where these leads contact the PC board. Iref (pin 12) and Q ref (pin 5), I (pin 11) and Q (pin 6) Inputs The I and Q inputs are designed for unbalanced operation but can be driven differentially with simi+5 V 1000 pF 1000 pF
lar performance. The recommended level of unbalanced I and Q signals is 2.5 Vp-p with an average level of 2.5 V above ground. The reference pins should be DC biased to this average data signal level (VCC/2 or 2.5 V typ.). For single ended drive, pins 5 and 12 can be tied together. For balanced operation, 2.5 Vp-p signals may be applied across the Imod/Iref and the Qmod/Qref pairs. The average level of all four signals should be about 2.5 V above ground. The impedance between any I or Q and ground is typically 10 K and the impedance between Imod and Iref or Qmod and Qref is typically 10 K. The input bandwidth typically exceeds 40 MHz. It is possible to reduce LO leakage through the IC by applying slight DC imbalances between Imod and Iref and/or Qmod and Qref (see section entitled "HPMX-2003 Using Offsets to Improve Lo Leakage"). All performance data shown on this data sheet was taken with unbalanced I/Q inputs. LO Input (pins 7 and 8) The LO input of the HPMX-2003 is balanced and matched to 50 For drive from an unbalanced LO, pin 7 should be AC coupled to the LO
+5 V 1000 pF
using a 50 transmission line and a blocking capacitor (1000 pF typ.), and pin 8 should be AC grounded (1000 pF capacitor typ.), as shown in figure 1. For drive from a balanced LO source, 50 transmission lines and blocking capacitors (1000 pF typ.) are used on both pins 7 and 8, as shown in figure 2. The internal phase shifter allows operation from 800 - 1000 MHz. The recommended LO input level is -12 dBm. All performance data shown on this data sheet was taken with unbalanced LO operation. RF Output (pin15) The RF output of the HPMX-2003 is configured for unbalanced operation. The output is internally DC blocked and matched to 50 , so a simple 50 microstrip line is all that is required to connect the modulator to other circuits. VCCL (pin 16) Pin 16 is the VCC input for the output stage of the IC. It is not internally connected to the other VCC pins. The external connection allows the addition of a small inductor (0 - 6 nH) to tune the output for minimum VSWR, depending upon the operating frequency.
1000 pF
OPTIONAL INDUCTOR 1 2 3 4 Qref Qmod LOin 1000 pF 1000 pF 5 6 7 8 16 15 14 13 12 11 10 9 DO NOT CONNECT Iref Imod
LOin+ LOin- 1000 pF Qref Qmod 1000 pF 7 8 10 9 1 16 15 14 13 12 11
OPTIONAL INDUCTOR
RF out
2 3 4 5 6
RFout
I ref Imod
DO NOT CONNECT
Figure 1. HPMX-2003 Connections Showing Unbalanced LO and I, Q Inputs.
Figure 2. HPMX-2003 Connections Showing Balanced LO and I, Q Inputs.
7-40
HPMX-2003 Typical Data Measurement
Direct measurement of the amplitude and phase error at the output is an accurate way to evaluate modulator performance. By measuring the error directly, all the harmonics, LO leakage, etc. that show up in the output signal are accounted for. Figure 3, below, shows the test setup that was used to create the amplitude and phase error plots (figures 12 and 13). Amplitude and phase error are measured by using the four channel power supply to simulate I and Q input signals. Real 2.5 Vp-p I and Q signals would swing 1.25 volts above and below an average 2.5 V level, therefore, a "high" level input is simulated by applying 3.75 V, and a "low" level by applying 1.25 V to the I and/or Q inputs.
Amplitude and phase are measured by setting the network analyzer for an S21 measurement at frequency of choice. Set the port 1 stimulus level to the LO level you intend to use in your circuit (-12 dBm for the data sheet). A 6-10 dB attenuator can be placed in the line to port 2 to prevent network analyzer overload, depending upon the network analyzer you are using. By adjusting the VImod and VQmod settings you can step around the I, Q vector circle, reading magnitude and phase at each point. The relative values of phase and amplitude at the various points will indicate the accuracy of the modulator. Note: you must use very low ripple power supplies for the reference, VImod, and VQmod supplies. Ripple or noise of only a few millivolts will appear as wob-
bling phase readings on the network analyzer. The same test setup shown below is used to measure input and output VSWR, reverse isolation, and power vs. frequency. VImod and VQmod are set to 3.75 V and the appropriate frequency ranges are swept. S11 provides input VSWR data, S22 provides output VSWR data. S21 provides power output (add source power to S21 derived gain). LO leakage data shown in figures 18, and 19 is generated by setting VImod = VQmod = VIref = VQref = 2.5 V then performing an S21 sweep. Since phase is not important for these measurements, a scalar network analyzer or a signal generator and spectrum analyzer could be used.
HP-8753C VECTOR NETWORK ANALYZER PORT 1 PORT 2
5V
VQmod
VER 1
HPMX-2003/5
LO C
Q
R V CC 5V
HP-6626A SYSTEM DC POWER SUPPLY (FOUR OUTPUTS)
H
C
C C OUT
2.5 V
VImod
I
R
Figure 3. Test Setup for Measuring Amplitude and Phase Error, Input and Output VSWR, Power Output and LO Leakage of the Modulator.
7-41
HPMX-2003 Typical Performance
45
50
42
DEVICE CURRENT (mA)
45
DEVICE CURRENT (mA)
39
40
36
35
33
30
30 -55 -35 -15 5 25 45 65 85
25 4 4.5 5 V CC (VOLTS) 5.5 6
TEMPERATURE (C)
Figure 4. HPMX-2003 Device Current vs. Temperature, VCC = 5 V.
Figure 5. HPMX-2003 Device Current vs. VCC, TA = 25C.
10
10 8
4.25 V 3.75 V
10
8
OUTPUT POWER (dBm)
6
8
OUTPUT POWER (dBm)
5.5 5.75 6
OUTPUT POWER (dBm)
4 2 0 -2 -4 -6 -8
3.25 V
6
6
3.0 V
4
4
2
2.75 V
2
0 -55 -35 -15 5 25 45 65 85
-10 4 4.25 4.5 4.75 5 5.25
0 -25 -20 -15 -10 -5 0
TEMPERATURE (C)
V CC (VOLTS)
LO INPUT POWER (dBm)
Figure 6. HPMX-2003 Power Output vs. Temperature at 900 MHz, LO = -12 dBm, VImod = VQmod = 3.75 V , VIref = VQref = 2.5 V, VCC = 5 V.
Figure 7. HPMX-2003 Power Output vs. VCC and I, Q Level at 900 MHz, LO = -12 dBm, VImod = VQmod, TA = 25C.
Figure 8. HPMX-2003 Power Output vs. LO Level at 900 MHz, VCC = 5 V, VImod = V Qmod = 3.75 V, T = 25C. A
5:1
5:1
2:1
1.8:1
4:1
OUTPUT VSWR
4:1
OUTPUT VSWR
INPUT VSWR
1.6:1
3:1
3:1
1.4:1
2:1 -55 C 85 C 1:1 750 850 950 1050
2:1 -55 C 1:1 750 85 C
1:1 1.2:1
850
950
1050
4
4.5
5 V CC (VOLTS)
5.5
6
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. HPMX-2003 LO Input VSWR vs. Frequency and Temperature, V = 5 V. CC
Figure 10. HPMX-2003 Output VSWR vs. Frequency and Temperature.
Figure 11. HPMX-2003 Output VSWR vs. VCC at 900 MHz, TA = 25C.
7-42
HPMX-2003 Modulation Accuracy (Sample Part)
1
OUTPUT AMPLITUDE ERROR (dB)
0.5
85 C -55 C
0
-0.5
-1 0 90 180 INPUT PHASE (DEGREES) 270 360
Figure 12. HPMX-2003 Amplitude Error vs. Input Phase at 900 MHz, VCC = 5 V, (VImod -2.5)2 + (VQmod - 2.5)2 = 1.25 V LO = -12 dBm. , 25C Curve Deleted for Clarit y.
4
OUTPUT PHASE ERROR (DEGREES)
2
0 -55 C
-2 85 C
-4 0 90 180 INPUT PHASE (DEGREES) 270 360
Figure 13. HPMX-2003 Output Phase Error vs. Input Phase at 900 MHz, VCC = 5 V, (VImod -2.5)2 + (VQmod - 2.5)2 = 1.25 V, LO = -12 dBm. 25C Curve Deleted for Clarity.
8
OUTPUT MODULATION ERROR (%)
6
85 C
4
2
-55 C 0 0 90 180 INPUT PHASE (DEGREES) 270 360
Figure 14. Modulation Error vs. Input Phase at 900 MHz, VCC = 5 V, (VImod -2.5) 2 + (VQmod -2.5)2 = 1.25 V, LO = -12 dBm. Percent Modulation Error is Calculated from the Values of Amplitude and Phase Error.
7-43
HPMX-2003 Single and Double Sideband Performance
Single sideband (SSB) and double sideband (DSB) tests are sometimes used to evaluate modulator performance. Figure 17, below, shows the test equipment setup that was used to create the SSB
and DSB output spectrum graphs (figures 15 and 16). The phase shift provided by the I and Q signal generators must be very close to 90 degrees and the amplitude of the two signals must be matched within a few millivolts or results will not accurately re-
flect the performance of the modulator IC. The I, Q signal generator must put out low distortion signals or the output spectrum will show high harmonic levels that reflect the performance of the signal generator, not the modulator.
HPMX-2003 Typical Sideband Performance Data
SSB: VIref = VQref = 2.5 V, VImod = VIref +1.25 sin (2 f t), VQmod = VQref + 1.25 cos (2 f t), f = 25 kHz DSB: VIref = VQref = 2.5 V, VImod = VIref +1.25 cos (2 f t), VQmod = VQref + 1.25 cos (2 f t), f = 25 kHz Symbol PLSB LOleak PUSB IM3 Parameters and Test Conditions Lower Sideband Power Output LO Suppression Upper Sideband Power Output Third Order Intermodulation Products Units dBm dBc dBm dBm SSB + 3 34 -32 NA DSB 0 31 0 -34
5 -5
OUTPUT POWER (dBm)
5 -5
OUTPUT POWER (dBm)
-15 -25 -35 -45 -55 -65 -75 899.9
-15 -25 -35 -45 -55 -65 -75 899.9
899.95
900 FREQUENCY (MHz)
900.05
900.1
899.95
900 FREQUENCY (MHz)
900.05
900.1
Figure 15. Single Sideband Output Spectrum. LO = -12 dBm at 900 MHz. The Test Setup is Shown in Figure 1 7.
HP-8657B SYNTHESIZED SIGNAL GENERATOR
Figure 16. Double Sideband Output Spectrum. LO = -12 dBm at 900 MHz. The Test Setup is Shown in Figure 1 7.
COS
VER 1
HPMX-2003/5
LO C
Q
R V CC 5V
HP-6626A SYSTEM DC POWER SUPPLY
HP-3245A UNIVERSAL SOURCE OPT 001 DUAL OUTPUTS WITH 90 DEGREE RELATIVE PHASE SHIFT
H
C
C C OUT
SIN
DSB
I
R
SSB HP-8595A SPECTRUM ANALYZER
Figure 17. HPMX-2003 Single/Double Sideband Test Setup.
7-44
HPMX-2003 Using Offsets to Improve LO Leakage
It is possible to improve on the excellent performance of the HPMX-2003 for applications that are particularly sensitive to LO leakage. The nature of the improvement is best understood by examining figures 18 and 19, below. LO leakage results when normal variations in the wafer fabrication process cause small shifts in the values of the modulator IC's internal components. These random variations create an effect equivalent to slight DC imbalances at the input of each (I and Q) mixer. The DC imbalances at the mixer inputs are multiplied by 1 at the LO frequency and show up at the output of the IC as LO leakage.
It is possible to externally apply small DC signals to the I and Q inputs and exactly cancel the internally generated DC offsets. This will result in sharply decreased LO leakage at precisely the frequency and temperature where the offsets were applied (see figure 18). This improvement is not very useful if it doesn't hold up over frequency and temperature changes. The lower curve in figure 18 shows how the offset-adjusted LO leakage varies versus frequency. Note that it remains below -45 dBm over most of the frequency range shown. In the 20 MHz range centered at 900 MHz, the level is closer to -55 dBm.
Figure 19 shows the performance of the offset adjusted LO leakage over temperature. Note that the adjusted curve is at a level below -50 dBm over most of the temperature range. The net result of using externally applied offsets with the HPMX-2003 is that an LO leakage level below -40 dBm can typically be achieved over both frequency and temperature. The magnitude of the required external offset varies randomly from part to part and between the I and Q mixers on any given IC. Offsets can range from -56 mV to +56 mV. External offsets may be applied either by varying the average level of the I and Q modulating signals, or by varying the voltages at the Iref and Qref pins of the modulator.
-20
-20
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
-35
-30
-50
-40
-65
-50
-80 -55 -35 -15 5 25 45 65 85
-60 650
750
850
950
1050
1150
TEMPERATURE (C)
FREQUENCY (MHz)
Figure 18. LO Leakage vs. Frequency Without DC Offsets (Upper Curve) and LO Leakage vs. Frequency With DC Offsets (Adjusted for Minimum LO Leakage at 900 MHz). TA = 25C, VCC = 5 V, VIref = VQref = 2.5 V, LO = -12 dBm.
Figure 19. LO Leakage With No DC Offsets vs. Temperature (Upper Curve) and LO Leakage With DC Offsets (Adjusted for Minimum Leakage at 25C) vs. Temperature (Lower Curve). Frequency = 900 MHz, VCC = 5 V, VIref = VQref = 2.5 V, LO = -12 dBm.
7-45
HPMX-2003 Modulation Spectrum Diagrams
Figure 20, below, shows the test setup that was used to generate the modulation spectrum diagrams that appear on the GSM, JDC and NADC applications pages of this data sheet. The major differences between the tests are summarized in the table below.
The modulation spectra are created by setting the function generator to the appropriate bit-clock frequency. The pattern generator is set to produce a pseudorandom serial bit stream (n = 20) that is NRZ coded. The pseudorandom bit stream which simulates the serial data in a digital phone is fed to the base-band processor that splits it into a two bit parallel Baseband Filter 0.3 GMSK (HP 8657B) = 0.5 /4 DQPSK (HP 8657D) = 0.35 /4 DQPSK (HP 8657D)
stream (I and Q) and then filters each according to the requirements of the digital telephone system being simulated. The I and Q signals from the baseband filter are then DC offset by 2.5 V using the op-amp circuit. The output of the modulator is monitored using a spectrum analyzer.
System GSM JDC NADC
Bit Clock Frequency 270 kHz 42 kHz 48.6 kHz
Channel (LO) Frequency 900 MHz 950 MHz 835 MHz
1
VER 1
HPMX-2003/5 Iref
H
C C
R
HP-8657B SIGNAL GENERATOR 835-950 MHz
LO
HP-8563E SPECTRUM ANALYZER
C C OUT C V CC 5V
Q R
2 Qref
HP-3314A FUNCTION GENERATOR /4DQPSK Q INPUT +5 V HP-3780A PRBS GENERATOR ALL R = 5 k CLOCK HP-8657B OR HP-8657D BASEBAND PROCESSOR DATA I Q OP-AMP: TL-084
Q + 2.5 V
* *
- + Qref = 2.5 V
I CHANNEL IS IDENTICAL
OP-AMP CIRCUIT (SEE ABOVE)
I + 2.5 V TO 1 2.5 V TO I ref Q + 2.5 V TO 2 2.5 V TO Q ref
Figure 20. Test Equipment Setup for Modulation Spectrum Diagrams.
7-46
HPMX-2003 GSM Applications
The GSM System GSM (Group Speciale Mobile) commonly refers to the European digital cellular telephone system standard. Digital cellular phones for the European market must conform to this standard. The GSM system is characterized by 200 kHz channel spacing and mobile to base transmit frequencies of 890 - 915 MHz. The primary modulation characteristics include 0.3 GMSK filtering of the I and Q signals and 270 kbps transmission rate. Critical Performance Parameters GSM standards require that the telephone exhibit RMS phase error 5 and peak phase error <20. The modulated output spectrum of the phone must lie within a "spectral mask" which defines maximum allowable radiation levels into adjacent and alternate
channels. Specifically, 200 kHz from the channel center frequency (f0), the output of the phone must be at least 30 dB below the peak output at f0. 400 kHz from f0 the output must be 50-60 dB below the peak output at f0 depending upon the class of radio. Refer to the GSM900 specifi-cations for more detailed information. HPMX-2003 Performance Typical RMS phase error level of 2 and typical peak levels of 8 makes the HPMX-2003 an excellent choice for GSM applications. The output spectrum falls easily within the GSM spectral mask, and the high power and simple output configuration mean lower components count, reduced size and higher system efficiency. Particulars of Use Many of the GSM application performance graphs shown in this data sheet were created using the test board shown in figure 21, below.
The only external components required by this IC are four chip capacitors. One capacitor is used as a DC block on the input transmission line. The second capacitor (at pin 8) provides an AC ground to one side of the differential LO input. The third and fourth capacitors (at pins 1 and 16) are for V bypass. CC The circuit board includes an inductive trace that can optionally be used to minimize output VSWR by placing a bypass capacitor at various points along the inductive line. Minimum VSWR for GSM applications is achieved by placing the capacitor as shown in the circle (inductance 2 nH). The IC has an internal blocking capacitor so the output is a simple 50 transmission line. An enlarged scale layout of the test board can be found on the last page of this data sheet.
VER. 1
HPMX-2003/5
LO C
Q
R
V CC 5V
H
C C C OUT
I
R
Figure 21. HPMX-2003 GSM Test Board.
7-47
HPMX-2003 Typical Performance Data
0 RES BW = 3 kHz VBW = 30 Hz SWP = 60.0 SEC.
RF OUTPUT POWER (dBm) RF OUTPUT POWER (dBm)
GSM Applications
0
RES BW = 3 kHz VBW = 30 Hz SWP = 60.0 SEC.
RF OUTPUT POWER (dBm)
0
RES BW = 3 kHz VBW = 30 Hz SWP = 60.0 SEC.
-50
-50
-50
-100 899
900 FREQUENCY (MHz)
901
-100 899
900 FREQUENCY (MHz)
901
-100 899
900 FREQUENCY (MHz)
901
Figure 22. HPMX-2003 GSM Modulation Spectrum at -40C.
2:1 8
Figure 23. HPMX-2003 GSM Modulation Spectrum at 25C.
0
Figure 24. HPMX-2003 GSM Modulation Spectrum at 85C.
0
OUTPUT POWER (dBm)
POWER > 1.5:1 6
OUTPUT POWER (dBm)
1.75:1
OUTPUT VSWR
7
-10
OUTPUT POWER (dBm)
-20
-20
-40
85 C -55 C
-55 C -30 25 C 85 C
1.25:1
< VSWR
5
-60 25 C -80 850
1:1 880
890
900
910
920
4 930
-40 850
875
900
925
950
875
900
925
950
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 25. HPMX-2003 Output VSWR and Power vs. Frequency, VCC = 5 V, LO = -12 dBm, VImod = VQmod = 3.75 V , Unbalanced, VIref = VQref = 2.5 V, TA = 25 C.
8
OUTPUT AMPLITUDE ERROR (dB)
Figure 26. HPMX-2003 LO Leakage vs. Frequency and Temperature (Without Offset Adjustment), VCC = 5 V, LO = -12 dBm, VImod = VQmod = VIref = VQref = 2.5 V.
1
Figure 27. LO leakage vs. Frequency and Temperature (With 25C Offset Adjustment), VCC = 5 V, LO = -12 dBm, VIref = VQref = 2.5 V.
4
OUTPUT PHASE ERROR (DEGREES)
OUTPUT POWER (dBm)
6
0.5
85 C
2
4
0
-55 C
0
-55 C
2
-0.5
-2 85 C
0 -25 -20 -15 -10 -5 0
-1 0 90 180 270 360
-4 0 90 180 270 360
LO INPUT POWER (dBm)
INPUT PHASE (DEGREES)
INPUT PHASE (DEGREES)
Figure 28. HPMX-2003 Power Output vs. LO Input Power at 900 MHz, VCC = 5 V, VImod = VQmod = 3.75 V Unbalanced, , VIref = VQref = 2.5 V, TA = 25C.
Figure 30. HPMX-2003 Vector Phase Error vs. Input Phase and Temperature at 900 MHz, VCC = 5 V, LO = -12 dBm, Unbalanced, VIref = VQref = 2.5 V. Note: Modulation spectrum test conditions as follows: VCC = 5 V, LO = -12 dBm at 900 MHz, VImod = V Qmod = 2.5 Vp-p, unbalanced, average level = 2.5 V, VIref = VQref = 2.5 V, bit clock rate: 270 kHz, baseband filter: = 0.3 GMSK. Figure 29. HPMX-2003 Vector Amplitude Error vs. Input Phase and Temperature at 900 MHz, VCC = 5 V, LO = -12 dBm, VIref = VQref = 2.5 V.
7-48
HPMX-2003 NADC Applications
The NADC System NADC (North American Digital Cellular) commonly refers to the digital sections of the IS-55 cellular telephone system standard. Dual mode (FM/TDMA) cellular phones for the North American market must conform to this standard. The NADC system is characterized by 30 kHz channel spacing and mobile to base transmit frequencies of 824 849 MHz. The primary modulation characteristics include /4 DQPSK filtering of the I and Q signals and 48.6 kbps transmission rate. Critical Performance Parameters System specifications require that the telephone exhibit RMS modulation error under 12% in the digital mode. The modulated output spectrum of the phone must lie within a "spectral mask" which defines maximum allowable radiation levels into adjacent and alternate channels. Specifically, total
power radiated into the either adjacent channel must be at least 26 dB below the mean output power. Total power radiated into either alternate channel must be at least 45 dB below the mean output power. Refer to the IS-55 specifications for more detailed information. HPMX-2003 Performance The typical RMS modulation error level of 4% makes the HPMX-2003 an excellent choice for NADC applications. The output falls easily within the NADC spectral requirements, and the high power and simple output configuration mean lower components count, reduced size and higher system efficiency. Particulars of Use Many of the NADC application performance graphs shown in this data sheet were created using the test board shown in figure 31, below.
The only external components required by this IC are four chip capacitors. One capacitor is used as a DC block on the input transmission line. The second capacitor (at pin 8) provides an AC ground to one side of the differential LO input. The third and fourth capacitors (at pins 1 and 16) are for VCC bypass. The circuit board includes an inductive trace that can optionally be used to minimize output VSWR by placing a bypass capacitor at various points along the inductive line. Minimum VSWR for NADC applications is achieved by placing the capacitor as shown in the circle (inductance 6 nH). The IC has an internal blocking capacitor so the output is a simple 50 transmission line. An enlarged scale layout of the test board can be found on the last page of this data sheet.
VER. 1
HPMX-2003/5
LO C
Q
R
V CC 5V
H
C C
MR
OUT
C
I
R
Figure 31. HPMX-2003 NADC Test Board.
7-49
HPMX-2003 Typical Performance Data
0 RES BW = 3 kHz VBW = 30 Hz SWP = 9.00 SEC.
RF OUTPUT POWER (dBm)
RF OUTPUT POWER (dBm)
NADC Applications
0
RES BW = 3 kHz VBW = 30 Hz SWP = 9.00 SEC.
RF OUTPUT POWER (dBm)
0
RES BW = 3 kHz VBW = 30 Hz SWP = 9.00 SEC.
-50
-50
-50
-100 834.85 835.00 FREQUENCY (MHz) 835.15
-100 834.85 835.00 FREQUENCY (MHz) 835.15
-100 834.85 835.00 FREQUENCY (MHz) 835.15
Figure 32. HPMX-2003 NADC Modulation Spectrum at -40C.
2:1 8
Figure 33. HPMX-2003 NADC Modulation Spectrum at 25C.
0
Figure 34. HPMX-2003 NADC Modulation Spectrum at 85C.
0
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
1.75:1
7 POWER >
-10
-20
OUTPUT VSWR
1.5:1
6
85 C -40 -55 C
-20 -55 C -30 25 C 85 C
1.25:1 < VSWR 1:1 815
5
-60 +25 C -80 810
830
845
4 860
-40 810
820
830
840
850
860
820
830
840
850
860
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 35. HPMX-2003 Output VSWR and Power vs. Frequency, VCC = 5 V, LO = -12 dBm, VImod = VQmod = 3.75 V, Unbalanced, VIref = VQref = 2.5 V, TA = 25 C.
10
Figure 36. HPMX-2003 LO Leakage vs. Frequency and Temperature (Without Offset Adjustment), VCC = 5 V, LO = -12 dBm, VImod = VQmod = VIref = VQref = 2.5 V.
0.5 -55 C
Figure 37. LO Leakage vs. Frequency and Temperature (With 25C Offset Adjustment), VCC = 5 V, LO = -12 dBm, VIref = VQref = 2.5 V.
5
OUTPUT PHASE ERROR (DEGREES)
8
OUTPUT POWER (dBm)
OUTPUT AMPLITUDE ERROR (dB)
0.25
2.5 85 C
6
0
0 -55 C
4
-0.25 85 C
-2.5
2
0 -25 -20 -15 -10 -5 0
-0.5 0 90 180 270 360
-5 0 90 180 270 360
LO INPUT POWER (dBm)
INPUT PHASE (DEGREES)
INPUT PHASE (DEGREES)
Figure 38. HPMX-2003 Power Output vs. LO Input Power at 900 MHz, VCC = 5 V, LO = -12 dBm, VImod = VQmod = 3.75 V, Unbalanced, VIref = VQref = 2.5 V, TA = 25C.
Figure 39. HPMX-2003 Vector Amplitude Error vs. Input Phase and Temperature at 900 MHz, VCC = 5 V, LO = -12 dBm, VIref = VQref = 2.5 V.
Figure 40. HPMX-2003 Vector Phase Error vs. Input Phase and Temperature at 900 MHz, VCC = 5 V, LO = -12 dBm, Unbalanced, VIref = VQref = 2.5 V.
Note: Modulation spectrum test conditions as follows: LO = -12 dBm at 835 MHz, VI = VQ = 2.5 Vp-p, unbalanced, average level = 2.5 V, VIref = VQref = 2.5 V, bit clock rate: 48.6 kHz, baseband filter: = 0.35, /4 DQPSK, VCC = 5 V.
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HPMX-2003 JDC Applications
The JDC System JDC (Japan Digital Cellular) commonly refers to the Japanese digital cellular telephone system standard. Digital cellular phones for the Japanese market must conform to this standard. The JDC system is characterized by 25 kHz channel spacing and mobile to base transmit frequencies of 940 - 960 MHz. The primary modulation characteristics include /4 DQPSK filtering of the I and Q signals and 42 kbps transmission rate. Critical Performance Parameters JDC standards require that the telephone exhibit RMS modulation error 12.5%. The modulated output spectrum of the phone must lie within a "spectral mask" which defines maximum allowable radiation levels into adjacent and alternate channels. Specifi-
cally, 50 kHz from the channel center frequency (f0), the output of the phone must be at least 45 dB below the peak output at f 0. 100 kHz from f0, the output must be at least 60 dB below the peak output at f0. Refer to the JDC specifications for more detailed information. HPMX-2003 Performance The typical RMS modulation error level of 4% makes the HPMX-2003 an excellent choice for JDC applications. The output spectrum falls easily within the JDC spectral mask, and the high power and simple output configuration mean lower components count, reduced size and higher system efficiency. Particulars of Use Many of the JDC application performance graphs shown in this data sheet were created using the test board shown in figure 41,below.
The only external components required by this IC are four chip capacitors. One capacitor is used as a DC block on the input transmission line. The second capacitor (at pin 8) provides an AC ground to one side of the differential LO input. The third and fourth capacitors (at pins 1 and 16) are for VCC bypass. The circuit board includes an inductive trace that can optionally be used to minimize output VSWR by placing a bypass capacitor at various points along the inductive line. Minimum VSWR for JDC applications is achieved by placing the capacitor as shown in the circle (inductance 0 nH). The IC has an internal blocking capacitor so the output is a simple 50 transmission line. An enlarged scale layout of this board can be found on the last page of this data sheet.
VER. 1
HPMX-2003/5
LO C
Q
R
V CC 5V
H
C C C OUT
I
R
Figure 41. HPMX-2003 JDC Test Board.
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HPMX-2003 Typical Performance Data
0 RES BW = 3 kHz VBW = 30 Hz SWP = 7.50 SEC.
RF OUTPUT POWER (dBm) RF OUTPUT POWER (dBm)
JDC Applications
0
RES BW = 3 kHz VBW = 30 Hz SWP = 7.50 SEC.
RF OUTPUT POWER (dBm)
0
RES BW = 3 kHz VBW = 30 Hz SWP = 7.50 SEC.
-50
-50
-50
-100 949.875
950.00 FREQUENCY (MHz)
950.125
-100 949.875
950.00 FREQUENCY (MHz)
950.125
-100 949.875
950.00 FREQUENCY (MHz)
950.125
Figure 42. HPMX-2003 JDC Modulation Spectrum at -40C.
2:1 8
Figure 43. HPMX-2003 JDC Modulation Spectrum at 25C.
0
Figure 44. HPMX-2003 JDC Modulation Spectrum at 85C.
0
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
1.75:1
OUTPUT VSWR
7
-10
-10
POWER > 1.5:1 6
-20
-20
1.25:1 < VSWR 1:1 920
5
-30
-55 C 25 C
-30
-55 C 25 C 85 C
940
960
4 980
85 C -40 920 940 960 980
-40 920
940
960
980
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 45. HPMX-2003 Output VSWR and Power vs. Frequency, VCC = 5 V, LO = -12 dBm, VImod = VQmod = 3.75 V, Unbalanced, VIref = VQref = 2.5 V, TA = 25 C.
8
Figure 46. HPMX-2003 LO Leakage vs. Frequency and Temperature (Without Offset Adjustment), VCC = 5 V, LO = -12 dBm, VImod = VQmod = VIref = VQref = 2.5 V.
1
OUTPUT AMPLITUDE ERROR (dB)
Figure 47. LO Leakage vs. Frequency and Temperature (With 25C Offset Adjustment), VCC = 5 V, LO = -12 dBm, VIref = VQref = 2.5 V.
6 85 C
OUTPUT POWER (dBm)
6
0.5 85 C 0
OUTPUT PHASE ERROR (dB)
3
4
0 -55 C
2
-0.5
-55 C
-3
0 -25 -20 -15 -10 -5 0
-1 0 90 180 270 360
-6 0 90 180 270 360
LO INPUT POWER (dBm)
INPUT PHASE (DEGREES)
INPUT PHASE (DEGREES)
Figure 48. HPMX-2003 Power Output vs. LO Input Power at 950 MHz, VCC = 5 V, VImod = VQmod = 3.75 V, Unbalanced, VIref = VQref = 2.5 V, TA = 25C.
Figure 49. HPMX-2003 Vector Amplitude Error vs. Input Phase and Temperature at 950 MHz, VCC = 5 V, LO = -12 dBm, Unbalanced, VIref = VQref = 2.5 V.
Figure 50. HPMX-2003 Vector Phase Error vs. Input Phase and Temperature at 950 MHz, VCC = 5 V, LO = -12 dBm, Unbalanced, VIref = VQref = 2.5 V.
Note: Modulation spectrum test conditions as follows: LO = -12 dBm at 950 MHz, VImod = VQmod = 2.5 Vp-p, unbalanced, average level = 2.5 V, VIref = VQref = 2.5 V, bit clock rate: 42 kHz, baseband filter: = 0.5, /4 DQPSK, VCC = 5 V.
7-52
HPMX-2003 Part Number Ordering Information
Part Number HPMX-2003 HPMX-2003 T10 Option No. of Devices 25 min. 1000 Reel Size tube 7"
Package Dimensions SO-16 Package
9.80 (0.385) 10.00 (0.394)
HPMX-2003 Test Board Layout
1000 pF +5 V 1000 pF OPTIONAL INDUCTOR
3.80 (0.150) 4.00 (0.158) 5.80 (0.228) 6.20 (0.244)
16 15 14 13 12 11 10 9 4.60 (0.181) 5.20 (0.205)
1 2 3 4 Qref 5 6 7 8 1000 pF
16 15 14 13 12 11 10 9 DO NOT CONNECT I ref Imod RFout
PIN: 12
3
4
5
6
7
8
0.10 (0.004) 0.20 (0.008) 0.35 (0.014) 0.45 (0.018)
Qmod 1000 pF LOin+ LOin-
0.45 (0.018) 0.56 (0.022)
1.27 TYP. (0.050)
1.35 (0.053) 1.75 (0.069) 0.15 (0.007) 0.254 (0.010) 4.60 (0.181) 5.20 (0.205)
8 0 0.64 (0.025) 0.77 (0.030)
Finished board size: 1.5" x 1" x 1/32" Material: 1/32" epoxy/fiberglass, 1 oz. copper, both sides, tin/lead coating, both sides.
Note: white "+" marks indicate drilling locations for plated-through via holes to the groundplane on the bottom side of the board.
NOTE: DIMENSIONS ARE IN MILLIMETERS (INCHES).
F
U o A
C
E
A
J
D C
P
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